Technical Field
The present disclosure relates to integrated circuit fabrication and packaging, and more specifically, to wafer bonding that incorporates boron and nitrogen in the bonding stack, and a three-dimensional integrated circuit system so formed.
Related Art
Complex three-dimensional integrated circuit (3Di) systems are commonly formed by bonding wafers including integrated circuits therein. That is, a pair of wafers including integrated circuits therein are mated and bonded together to form a single larger 3Di system. Wafer-to-wafer bonding is advantageous because it provides for higher productivity compared to creating single, larger chips, and it allows for tighter pitch interconnect between chips that can be fabricated with separate technologies specifically optimized for their functionality (e.g., separately optimized memory and processor chips). One challenge of wafer-to-wafer 3Di integration is ensuring a high quality bond interface between the wafers so the wafers properly interconnect and are reliable. Some typical requirements for good bonding include: low temperature bonding (e.g., less than 350° C.) so that the bonding process does not adversely impact the integrated circuits in the wafers; mechanical strength so the bonding does not come apart; and good thermal conductivity to prevent overheating of the coupled wafers.
There are a number of wafer-to-wafer bonding techniques currently in use. The prevalent bonding technique, referred to as SiOx bonding, employs a low temperature oxide (LTO) (e.g., silicon oxide (SiOx (denoted as SiOx herein)) for the bonding surface on each wafer. During this process, each wafer has an LTO layer formed thereon. The LTO layer is planarized, and may be activated with a plasma etch and rinsed. The wafers are then aligned and brought into contact to initially bond them at room temperature, followed by an anneal to permanently bond the wafers together. While the above-described SiOx bonding process is more advantageous than other current techniques, e.g., copper or adhesive bonding, the SiOx bonding has a number of disadvantages, including, for example: relatively low thermal conductivity that presents a challenge for systems that include multi-stacking of high input/output memory wafers and/or high-power logic wafers. Where more than two wafers are stacked or high-power is involved, the wafers tend to operate at higher temperatures, making high thermal conductivity more important. Further, SiOx bonding has relatively low cohesive bonding energy (e.g., <2.7 Joules per square meter (J/m2)), which may pose challenges for reliability and chip-package interaction (CPI). SiOx bonding is also disadvantageous because it does not present a good barrier to copper diffusion, thus necessitating use of other layers to prevent copper diffusion from integrated circuits in the wafers.